Modeling of FPGA-based Pulse-Width Modulation for Parallel Three-phase AC/DC Converters

S.R.S. Raihan

Graduate Student Member, IEEE Dept. of Electrical Engineering

University of Malaya Lembah Pantai, 50603 Kuala Lumpur,

Malaysia

N.A. Rahim

Senior Member, IEEE Dept. of Electrical Engineering

University of Malaya Lembah Pantai, 50603 Kuala Lumpur,

Malaysia

Abstract- This paper presents the modeling of pulse-width modulation (PWM) that is based on Altera Cyclone II FPGA device by using Altera DSP Builder and Matlab Simulink software. The PWM signals are implemented for parallel three-phase AC-DC flyback converters. Each converter module consists of three switches and a freewheeling diode that prevents the current from circulating in the bridge circuit during the device’s turn-off. Among various PWM techniques, the design uses sinusoidal PWM. The three-phase sinusoidal signals are compared with a triangular carrier signal to generate the gate signals of the AC/DC switches. Simulation results of the generated PWM signals and the total harmonic distortions are presented.

I. INTRODUCTION

Flyback converter is one of the simplest forms of DC converters. The principle operation is similar to buck-boost converter where the DC output could vary from zero up to multiples of the DC supply. The flyback circuit topology has attracted interest from many researches when utilizing AC as an input source [1]-[4]. However, the drawbacks of flyback converter are high ripple output voltage, poor regulation, and low-power DC conversion.

Converters connected in parallel are more advantageous than a single converter is in terms of reliability and efficiency [5]. By connecting two AC/DC converters or rectifiers in parallel, output voltage ripples and voltage regulation can be improved. Parallel converters provide better flexibility in modular system design and system reconfiguration [3] [6].

Various pulse-width modulation techniques, different in concept and performance, are widely used to control the output of power converters. Sinusoidal PWM, hysteresis PWM, space vector modulation (SVM), and optimal PWM techniques based on performance criteria are some of the widely used strategies [2][7]-[9]. Sinusoidal PWM, where a sinusoidal modulating signal is compared with a triangular carrier signal to generate gate signals of the converter switches, can be implemented easily by using analog techniques. However, the use of analog comparators does not produce a fixed relation between the carrier signal and the reference signal but will introduce sub-harmonics into the system [10]. Recent developments have made it possible to generate sinusoidal PWM digitally. In this paper, a modified sinusoidal PWM, capable of minimizing harmonics present on the AC side of the converter system, is

implemented by using a field programmable gate array (FPGA) [2].

II. DESIGN

Fig.1 shows the basic structure for generating digital PWM. The look-up table contains the reference sinusoidal waveform. Fig. 2 shows the reference voltage compared with a high-frequency triangular carrier wave. The comparator output forms the switching state of the corresponding rectifier leg.

For the complete system shown in Fig. 3, three PWM patterns will be generated for all three phases. Each rectifier contains three IGBT switches. These switches are controlled by the switching pattern produced by the PWM generator as shown in Fig. 4. Altera Cyclone II FPGA is used as the platform for generating PWM signals.

Figure 1: A typical block diagram of a PWM generator

0 0.002 0.004 0.006 0.008 0.01 0.012 0.014 0.016 0.018 0.020

0.5

1

1.5

2

0.002 0.004 0.006 0.008 0.01 0.012 0.014 0.016 0.018 0.02

-0.2

0

0.2

0.4

0.6

0.8

1

1.2

Time

PWM signal

modulating signalcarrier signal

Figure 2: Generating PWM signal using sinusoidal PWM technique

The triangular carrier is generated digitally by using an

UP/DOWN counter. The counter is clocked by a clock generated by the internal phase-locked loop (PLL) of the FPGA. The relationship between the carrier frequency and the main clock frequency of the UP/DOWN counter is

2)12( ⋅−=

nclk

cf

f (1)

where fc is the carrier frequency, fclk is the main clock frequency, and n is the number of bits of the UP/DOWN counter. In this model, an 8-bit UP/DOWN counter will generate a carrier wave of approximately 19.6 kHz from the main clock frequency of 10MHz. The sinusoidal waveform uses 60o look-up table, where 60 sampled data is stored into the EPROM. A MOD60 counter acts as a pointer for these data. The amplitude of the carrier wave is fixed at 255 while the amplitude of the modulating wave can be varied by multiplying the look-up table data with input from the user.

powergui

Discrete,Ts = 1e-006 s

Voltage Measurement 3

v+-

Three -Phase Source

A

B

C

Three -PhaseV-I Measurement

IabcA

B

C

a

b

c

Scope 3

R

PWM generator

phaseA

phaseB

phaseC

Multimeter

3

EMI Filter

AAo

ut BB o

ut C

Cou

t

Diode 12

Current Measurement 3

i+ -

C1

AC/DC Converter 2

PWM A

PWM BPWM C

A

Out1C

Out

B

AC/DC Converter 1

PWM A

PWM B

PWM CA

Out1C

Out

B

Transformer

1 2

Figure 3: The overall system of parallel three-phase flyback converters

in Matlab Simulink

PWM_C3

PWM_B2

PWM_A1

pinS 3

S3Pin _L7

pinS 2

S2Pin _F6

pinS 1

S1Pin _H6

carrier 1

Mcarrier1

clk20

Wcarrier2

Sine generator

In1

PHASE _A

PHASE _B

Signal Compiler

S3

obit

S2

obit

S1

obit

PWM

CNT (7:0)ABC

PWM_A

PWM_B

PWM_C

PWM_123

PLL

Logical Bit Operator

OR

Delay 2

z-1

Delay 1

z-1

Delay

z-1

Cyclone II EP 2C70 DSP Development Board

Counter

clk_ena q(7:0)mod 180

Comparator 1

a

b<=

Comparator

a

b<=

Clock

10 ns

Figure 4: Modeling of PWM generators in Altera

DSP Builder/Matlab Simulink

Figure 5: Signal Compiler

The Signal Compiler block as shown Fig.5 is added to the

model for analyzing and synthesizing the design. A netlist,

containing information of logic gates and their interconnections, will be created and will be used to realize the target circuit in the hardware. The fitting process in the compiler will map the design into the target before placing the parts and routing the paths between the components based on the specified timing requirements. Once the fitting process is completed, the design is ready to be programmed into the FPGA.

III. RESULTS

The output of the PWM generator produces three PWM patterns (see Fig. 6). Fig. 7 shows the PWM waveforms generated by Altera Cyclone II FPGA. The simulated PWM signals are applied into the parallel three-phase flyback converters. Fig. 8 shows the AC source voltage and current which are almost in phase. The harmonic spectra for each waveform are shown in Figures 9, and 10, respectively. The THD of the input voltage and the input current are 2.81%, and 1.38%, respectively.

Figure 6: Generated PWM patterns in Matlab Simulink

Figure 7: Experimental result for three PWM waveforms generated from

Altera Cyclone II FPGA

0 0.005 0.01 0.015 0.02 0.025 0.03 0.035 0.04 0.045 0.05-400

-300

-200

-100

0

100

200

300

400

Time

voltage

current

Figure 8: AC voltage and current of parallel flyback converters in Matlab

Simulink

Figure 9: THD of the input voltage is 2.81%

Figure 10: THD of the input current is 1.38%

IV. CONCLUSION

Modeling of parallel three-phase flyback converters as well as PWM generator, based on Altera Cyclone II FPGA configuration, has been developed in Matlab Simulink environment. Simulation results are provided and the experiment result of the generated PWM signals is presented. FPGA is shown to offer the flexibility to reconfigure the design of a PWM circuit without modification to hardware.

ACKNOWLEDGMENT

This work was supported by University of Malaya under RG057/09AET. The authors would like to thank UMPEDAC, University of Malaya.

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sinusoidal supply currents.” IEE Proceedings-B. (1991), pp.143-151. [2] Omar, A. M., Rahim, N.A., and Mekhilef, S. "Three-phase

Synchronous PWM for Flyback Converter With Power-Factor Correction Using FPGA ASIC Design." IEEE Transactions on Industrial Electronics, 2004, 51(1), pp. 96-106.

[3] Sangsun, K. and P. N. Enjeti. "A parallel-connected single phase power factor correction approach with improved efficiency." IEEE Transactions on Power Electronics, 2004, 19(1), pp. 87-93.

[4] Fanghua, Z. and Y. Yangguang. "Novel Forward-Flyback Hybrid Bidirectional DC-DC Converter." IEEE Transactions on Industrial Electronics, 2009, 56(5), pp. 1578-1584.

[5] Baumann, M., and Kolar, J.W. "Parallel Connection of Two Three-phase Three-switch Buck-Type Unity-Power-rectifier Systems with DC-Link Current Balancing." IEEE Transactions on Industrial Electronics, 2007, 54(6), pp. 3042-3053.

[6] Pan, C.-T. and L., Y-H. "Modeling and Coordinate Control of Circulating Currents in Parallel Three-Phase Boost Rectifiers." IEEE Transactions on Industrial Electronics, 2007, 54(2), pp. 825 - 838.

[7] Inagaki, K., T. Furuhashi, et al. "A new PWM control method for AC to DC converters with high-frequency transformer isolation." IEEE Transactions on Industry Applications, 1993, 29(3): 486-492.

[8] Vlatkovic, V. and D. Borojevic. "Digital-signal-processor-based control of three-phase space vector modulated converters." IEEE Transactions on Industrial Electronics, 1994, 41(3): 326-332.

[9] J. Holtz, “Pulse-width modulation for electronic power conversion,” Proc. IEEE, vol. 82, pp. 1194-1214, Aug. 1994.

[10] Terörde, G. (2004). Electrical Drives and Control Techniques, ACCO Publishing.