Lab2 Ahmad Al Zubir Zulkifly

7/31/2019 Lab2 Ahmad Al Zubir Zulkifly

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FACULTY OF ELECTRICAL ENGINEERING

UNIVERSITI TEKNOLOGI MARA

MALAYSIA

ELE 653

LAB 1

Synthesis Lab

TASK 1

PREPARED BY:

AHMAD AL-ZUBIR BIN ZULKIFLY 2009435996

GROUP:

EE2108A

LECTURER:

Puan Siti Lailatul Mohd Hassan


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3.0. How Synthesis Work

Figure 1: Process of Synthesis.


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4.0. Method Basic Synthesis Flow

Figure 2 : Basic Synthesis Flow Chart.

START

Go to directory task1

Read & Link Desi n

DC Setu

Design Constraints

Save the Desi n

Optimize Design

Analyze Design

END

Figure 3 : Flow Chart of Task


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5.0. Resulta) DC Setup

Figure 4: A Setup File That Specifies The Standard Cell Library.


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b) Read & Link Design

Figure 5: DC Commands to Verify Library Settings.


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Figure 6: Block Diagram of Counter.

Figure 7: Schematic View of The RTL Code.


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c) Design Constraints

Figure 8: DV Command Prompt Using TCL Syntax.

d) Optimize Design

Figure 9: Schematic RTL was Changed After Optimized.


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e) Save the Design

Figure 10: DV Command Prompt Use To Save The Design.

f) Analyze Design

Figure 11: Report Area of The Design Counter.

Figure 12: Report Clock of The Design Counter.


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Figure 13: Report Clock_Skew of The Design Counter.

Figure 14: Report Timing of The Design Counter.


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TASK 2 DC Setup

Firstly we create the constraints file. These are similar constraints to Task 1. Then

we check any syntax errors and there are no errors, dcprocheck will return thefollowing message below:

Figure 15: The the constraints file of the Design Counter.

Read & Link Design -> Design Constraints -> Optimize Design -> SaveDesign

Figure 16: Script commands of the Design Counter.

Figure 17: Script commands of the Design Counter.


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a) Analyze Design

Figure 18: Report Area of Counter

Figure 19: Report Clock and Report of Clock_Skew of Counter.


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Figure 20: Report timing of of The Design Counter.


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From Figure 15 showed The the constraints file of the Design Counter. These are

similar constraints to task 1 but we save in scripts/constraints.tcl. Afterwe run the command

there are no errors, dcprocheck will return the following message like Figure 2.

From Figure 16 and Figure 17 showed Script commands of the Design Counter. In

this sectionwhich will read in the design, apply the constraints, compile the design, generate

reports and exit the tool.

From Figure 20 showed Report Timing of The Design Counter. We get the value of

slack (MET) same as manual is 1.061.

7.0. ConclusionFor the conclusion, it can be conclude that all the objective has been fulfill. This lab

makes student to more competible using a Synopsys software. We learn how to simulation

using Synopsys DC using DC's graphical user interface tool called Design Vision. Thus, we

also know and learn verilog code for simple counter.

So with study and learn Task 1 and Task 2, we can fimiliar and friendly with Synopsys

Eda Tools.

Lab2 Ahmad Al Zubir Zulkifly

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