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Characterization of Strained Silicon MOSFET UsingSemiconductor TCAD Tools

Wong Yah Jin, Ismail Saad and Razali IsmailFaculty of Electrical Engineering,Universiti of Teknologi Malaysia,81300 Skudai, Johor, Malaysia.

Email: helommi(igmalxom ismail s(ums.edu.myand razal(i0


substrate. Next a silicon germanium (SiGe) layerwith 0.35 Ge concentration is deposited on thesilicon layer, followed by the deposition ofanother silicon layer with 0.007um thickness onto the SiGe layer. After the deposition, strainedsilicon is created at the channel. Polysilicon isthen deposited and patterned to form the gate.The process continues with the implantation ofsource/drain. The boron is implanted with the1.0 x 1015 cm-2 doping concentration. Next thesilicon nitride (Si3N4) layer is deposited andpatterned to cover the gate, source and drain.Then the aluminum is deposited and patterned toact as the metal contact. Finally, the finalstructure of the strained silicon PMOS is createdas shown in Figure 1(a).

The conventional PMOS structure is shownin Figure 1(b). The difference between theconventional structure with the SSPMos structureis that there is no added SiGe layer, thin Si layerand Si3N4 capping layer.

Fig. 1(a): The strain silicon PMOS device structure.

source drain Gitad

....................................................................................................................................................................................................................... ....

Fig. 1(b): The PMOS device structure.

The SSPMos structure is created with 0.0160ptmgate oxide thickness and 0.71ptm channel length.Meanwhile the conventional PMOS structure iscreated with 0.0091ptm gate oxide thickness and2.5ptm channel length.

III. DEVICE DOPING PROFILE

Figure 2 shows the net doping and Geconcentration profile for the SSPMos. This is theresult from the Athena simulation by performinga vertical cutline which starts at the gate andstops at the substrate. From Figure 2, we can seethat the boron doping is high at the gate with 1 x1020 cm-3 doping concentration. There is nodoping in the silicon dioxide layer. Meanwhilethe phosphorus doping at the strained silicon,SiGe layer and substrate is 1 x 1016 cm-3. Fromthe figure, the composition x shows a 0.35 of Geconcentration in silicon germanium layer only.

GateZ7r-----TW--

Xil 01

oxide layer

strain silicon layer-. NO Dping(k

silicon4 --grmanium layer

substratearea

Fig. 2: The net doping and Ge concentration profilefor

SSPMos.

IV. ELECTRICAL CHARACTERIZATION

In device simulation, both the strainedsilicon structure and the conventional PMOSstructure are simulated in Atlas. The devices aresimulated to obtain the characteristics of theconventional PMOS and strained silicon PMOS(SSPMos). The mobility models that are used toobtain the electrical characteristics are theparallel electric field dependence andconcentration dependent model. Beside that, thecarrier static lifetime for the Si material is set atle-7 tau for electron and hole. Meanwhile theSiGe material is set to le-8 tau for electron andhole. For the carrier statistic model, the bandgapnarrowing and Boltzman are chosen in thissimulation. As for the recombination models, theauger and SRH concentration dependentlifetimes are chosen. The characteristics of thedevices that was obtained from the simulation arethe drain current versus gate voltage curve,

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threshold voltage, drain induced barrier lowering(DIBL) and drain current versus drain voltagecurve.

From the simulation, the drain current, Idversus gate voltage, Vgs curve with a drainvoltage, Vds of -0.1V for both conventionalPMOS and the SSPMos devices are shown inFigure 3. From Figure 3, it is obvious that thedrain current for SSPMos structure is higher thanconventional PMOS. This indicates that theSSPMos has higher drive current compared toconventional PMOS. Meanwhile the extractedthreshold voltage parameters from Figure 3 are -0.511299V and -0.92902V for the SSPMos andconventional PMOS respectively. This indicatesthat the strained PMOS has lower voltagethreshold than the conventional PMOS whichtranslates to lower power consumption.

The drain current versus gate voltage

v h E-oV s -1

Th IL fo th XXStrained PMOS i .04 n

cPMOS nv ina SPMSosrtd voltage.V2.O tE-O-3

-2.5 -2 -1.5 -1 -05 o 0.5atevoltage, Vgs

Fig.3: The comparison of draincusrent versus gatevoltage graph when Vds isgaI OfV a

Next, the drain induced barrier lowering,(DIBL) parameter is obtained from the differencebetween the threshold voltage divided by -2.8V.The DIBL for the strained PMOS is 0.3034V andthe conventional PMOS is 0.4747V. The DIBLfor the strained PMOS is smaller than theconventional PMOS. This shows that the strainsilicon for PMOS is better compared to

e i conventional PMOS.Beside that, both structures are simulated to

ramp the drain voltage, Vds to -3.3V when thegate voltage, Vgs is bias to -1lIV, -2.2V and -3.3V. The simulation results are presented inFigure 4 which represents the graph of the draincurrent versus the drain voltage. From Figure 4,it can be seen that the strained PMOS device hasa higher drive current compared to theconventional PMOS. From these results, it isevident that the strained silicon PMOS has abetter drive current than conventional PMOS.

The drain current versus drain voltage

-3.5 -3 -2.5 -2 -1.5

Drain voltage, Vds

-05 0

Fig. 4: The comparison of drain current versus drainvoltage graph when Vgs is - 1. 1V,-2.2V and-3.3V.

V. Conclusion

From the results, it can be seen that thestrained silicon has a better performancecompared to the conventional PMOS eventhough the channel length for the strained siliconis larger than the conventional PMOS. Thisresearch will continue to study the electricalcharacteristics of the SSPMos such as theeffective mobility enhancement. Furtherimprovements and optimization will be done tothe device performance in order to achieve asignificant enhancement on MOSFET. Strainedsilicon is still considered as a new technologyand more research is still needed to improve itsimplementation to the current technology.

REFERENCES

[1] Silvaco International (2005). Athena andAtlas User's Manual Process SimulationSoftware. USA: Silvaco International.

[2] Taur Y. and et. al. IDEM Technical Digest.1998. pg 789.

[3] Cho, H., Park, B. G. and Lee, J. D. Nano-Scale SONOS Memory with a Double GateMOSFET Structure. Journal of the KoreanPhysical Society. Feb 2003. 42(2):233-236.

[4] Yuan J., Zeitzoff P. M. and Jason Woo C.S.Source/Drain Parasitic Resistance Role andElectrical Coupling Effect in sub 50 nmMOSFET Design. ESSDERC. 2002. pg 503-506.

[5] Acosta T. and Sood S. Engineering StrainedSilicon-looking Back and Into the Future.IEEE Potentials. IEEE. 2006. 25(4):31-34.

[6] Ismail K., Meyerson B.S. and Wang P.J.High Electron Mobility in Modulation dopedSi/SiGe. Application Physics Letter. IEEE.1991. 58(19):2117-2119.

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.!k Strained PMOS1.1v

....HH Strained PMOS2.2V

m. Strained PMOS3.3V

x PMOS -1. v

x PMOS -2.2V

o PMOS -3.3V



[7] Thompson, S.E., Armstrong, M. and et.al. A90nm Logic Technology Featuring StraiendSilicon. IEEE Transaction on ElectronicDevices, 2004. IEEE. 2004. 51(11):1790-1797.

[8] Thuy Dao. Process Induced Damage: WhatChallenged Lie Ahead?. IEEE. 2003. 51-55.

[9] Wang, H.C., Wang, P.C. and et.al. Substratestrained silicon technology: ProcessIntegration. IEEE International ElectronicDevice Meeting, 2003. IEEE. 2003. 3.4.1-3.4.4.

[10] S.H. Olsen, M. Temple and et.al. DoublingSpeed using strained Si/SiGe CMOStechnology. Thin Solid Films. Elsevier. 2005.508(1-2): 338-341.

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