2005AASIAP0R((KOWENGONAPPIEDTa ROOAiDGPRO(,December 20-21, 2005, Johor Bahru, Johor, MALAYSIA

Parameter Based Investigation: The Design ofNode-B High Power PA

Wan Nasra W. F.', Mahamod 1.2, Azzemi A.', and Mohd. Fadzil A.'

'TM Research & Development Sdn. Bhd.Idea Tower, UPM-MTDC, 43400 Selangor, Malaysia

2Faculty ofEngineeringUniversiti Kebangsaan Malaysia43600 Bangi, Selangor, Malaysia

Abstract-This document is an introductory report onthe design of a W-CDMA high-power PA. Itconcentrates on understanding the PA specifications;and translates them into a working prototype. Theintended area of application is 3G Node-BTransmitter System. The design shall be able to meetthe stringent QPSK behavior and will operatebetween 2110 to 2170 MHz. It shall be able toproduce a maximum of +46 dBm output power toconform to Wide Area Base Station category. It shallalso satisfy the test requirements listed for W-CDMA.

1. Introduction

The high-power PA is required for operationwith FDD W-CDMA transceiver system. Thisdocument consists of five main sections. The firsttwo sections contain tabulated information on thestandards being used for this high-power PA design.The next two sections cover the complete designmethodology, requirements and architectureconsiderations. Finally, the conclusion is given in thesixth section.

2. W-CDMA Specifications

The W-CDMA specifications being applied tothe current design is shown in Table 1. It conformsto the 3GPP document, TS 25.104 [1], [21. Boththese documents will be used to develop thespecifications for the desired high-power PA. Theresults will be shown in section 5.The project goal is to produce a working high-powerPA (HPPA) prototype. In order to aid thedevelopment of the HPPA specifications, the end-product is visualized to be a complete 3G wirelesscommunication transceiver prototype. This prototypehas been divided into four different workingmodules, which consist of a 3G RF Transmitter,3GRF Receiver, 3G RF Front End and a 3G High

Power PA. All modules must conform to thespecifications listed in Table 1.

Table 1: Wireless Standard Applicable to HPPA Design[Agilent Technologies, Inc., May 20051

Parameters Specifications

Description Wideband Code DivisionMultiple Access (FrequencyDivision Duplex)

Geography WorldwideFrequency Range Band I

1920 to 1980 MHz (UL)2110 to 2170 MHz (DL)

Multiple Access CDMATechnologyModulation and Filter QPSK, RRC FilterType (a = 0.22)Channel Spacing 5 MHzSymbol Rate 3.84 McpsSingle User Data Rate 384 kbps (single code)Frequency Reuse I x IPaftem (cell x sector)Switching Method Packet and DataSpeech CODEC Adaptive

Multi-rateStandard Development 3GPPOrganization www.3gpD.org

3. High Power PA Standard Test Conditions

This section will list down the test conditionsand parameters required to produce a working HPPAprototype. It will serve as the starting point fordesigning the PA module. Note that in this section,only HPPA test conditions will be listed.

There are ten types of tests the HPPA must pass.They consist of a DC Test (1), an RF Test (1) and aWCDMA Conformance Test (8). These testconditions directly define the specifications for theHPPA design (Table 2).

Having taken into account these specifications,the building blocks of the PA can now be put

0-7803-9431-3/05/$20.00 02005 IEEE. 274

together. The main concem here is the high outputpower (+46 dBm). Another concem is theoutrageously demanding power compression point,which is +54 dBm. The final concem is the linearityof the PA. Care must be taken so that power outputby the HPPA during operation does not go beyondthe compression point. It must also not spill-over intothe adjacent channel.

Table 2: High Power PA W-CDMA Specifications.

HPPA DC Specifications

Voltage supply, VddCurrent Consumption, I&JDC Power Dissipation, PDC

Efficiency, iqHPPA RF Specifications

FrequencyPoutP1dBOP3Gain

Retwn LossesPAE

HPPA WCDMA Conformance SpecificationsACLRCCDF

Code Domain PowerEVM

Occupied BandwidthMaximum Output Power

Tlhe challenge is to develop a PA that cansupport such a high power compression point andmeet the desired specifications.

4. Power Amplifier Architecture

The next step is to decide on the architecture forthe HPPA. The result of the survey can be seen inTable 3. From the comparison, a balancedarchitecture was chosen for this HPPA design forreasons related to power output, signal impairmentsand linearity; which will be explained in section 5.

Table 3: Commercial BS PA Architectures.

Manufacturer PA Pout (dBm)Architecture

FIT (F-PA-IMA-3012) Single Ended +35 dBmHittite (HMC-C008) Cascade +42 dBmPhilips Semiconductor Balanced +47 dBm(50 Watt, CDMA AmplifierAmplifier Solution)

The generic balanced amplifier block diagram isshown in Figure 1. This architecture is most suitablefor IC design whereby all the components can be

easily integrated into a module. Theoretically, itallows mismatch from the amplifiers to pass backthrough the couplers. The mismatches appear in anti-phase and therefore cancels at the RF input andoutput port.

Figure 1: Balanced Amplifier Topology.

Even though it requires double the number ofcomponents than single ended topology, the use ofquadrature couplers results in essentially perfectinput and output matching. This is feasible for thereflective nature of the individual amplifiers.Another advantage is the effective powercombination, resulting in easier chip selection for themain amplifier.When the architecture has been decided, the next

step is to choose the main amplifier chip. Twodurable high power amplifier chips from FreescaleSemiconductor Inc. were compared. Both chips wereproduced from Freescale's LDMOS E-Mode FET.The result is shown in Table 4.

Table 4: Chip Comparison for HPPA BalancedArchitecture.

Specifications M:RF5S21 150HR3 MRF21125Application UMTS WCDMAGain, dB 12.5 13.0Power output, dBm 45.2 43.0Compression point, 51.0 51.0dBmDrain Efficiency, % 25 18ACLR, dBc 39 45Supply Voltage, V 28 28Supply Curent, mA 1300 1600

To get +46 dBm output from the balancearchitecture, we need +43 dBm output from the mainamplifier (Figure 1). Consequently, the FETs inTable 4 need to be driven at a higher margin.Therefore, MRF5S21 150HR3 is chosen for thisapplication due to the fact that it has 2 dB outputpower margin compared to its counterpart.

Next, the amplifier chip must be biased to ensurethe FET is operating at the required cufrent andvoltage. The biasing information was extracted fromthe MRF5S21 150HR3 datasheet. The optimumbiasing values are as follows: VDs = 28 V, IDQ =1300 mA and f = 2.14 GHz. Gate bias voltage,

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VGs, was obtained through ADST. simulation(Figure 2, next page).

From Figure 2, this FET must be provided withVGs supply between 3.6 to 7.2 V for class ABoperation. To get maximum output voltage swig,the chosen VGS is 3.97 V. The simulated results werestill within the operating range ofthe manufacturer'sdata.

25

.m8

15-

10- VGS36 VGSV2JF.360-0 T,2C2

m70 5 10 15 20 25 30VGS

Figure 2: MRF5S21 150HR3 DC Transfer Characteristicat Vd, = 28 V.

The final design step was to match the input andoutput port of the amplifier. To do this, the stabilitycondition of the amplifier must first be obtained. Toget the stability condition, the S-Parameters must beknown. This infonnation was extracted from thedatasheet. The corresponding S-Parameters at thecentre design frequency are shown in Table 5.

Table 5: MRF5S21 150HR3 S-Parameter Condition

S-Paraneter ValueSIl -0.912+jO.304S22 -0.972 +jO.076S21 0.502-jO.156S12 8.395e-6 -jO.002

Two methods were used to determine the

amplifier stability. The first one is by ADSTmsimulation. The other method is the online calculatoranalysis from Daycounter, Inc. Table 6 shows theresults from ADSTm simulation and Daycounter Inc.There is a discrepancy of 0.2 dB between bothresults. However, this discrepancy is still acceptable.

Table 6: Stability Analysis for HPPA BalancedArchitecture

With reference to Table 6, it can be concludedthat the amplifier is stable. This condition is true forK greater than 1.2. Therefore, no stability correctionis needed. Finally, the input and output matchingnetwork were constructed. The couplers were alsoconstructed prior to full design simulation. Thecouplers are microstrip couplers using substratematerial Rogers 43500. A complete balanced HPPAcircuit was then simulated using ADSTm and itsresult will be discussed in the following section.

5. Results and Requirement Justifications

5.1 Output Power at 1-dB GainCompression Point (PIdB)From Table 2, the power output for the PA is

specified as +46 dBm, 3 dB above the total transmitpower. This qualifies the system, when it isimplemented in a base station, to transmit in theWide Area Base Station category [3], [4]. Note that+46 dBm is the operating output power, not thecompression point. The maximum allowable poweroutput by the PA is, however, +54 dBm. This is tosatisfy the 8 dB peak-to-average power ratio (PAPR)requirement.

As long as the PA output power does not exceed+54 dBm, then the system is operating in its linearregion. The other parameters (in Table 2) will also beat their acceptable level, if not better. It can be seenin [5], [61 that most of the transmitter relatedmeasurement revolves around managing the poweroutput from the system. Its limitations are thelimitations of the PA itself. Hence the importance ofthe final PA.

50-A ,f** ,,8

30_ ¶ p

to~~~~~~~f

Figure 3: Spectral Re-growth Phenomena.

Figure 3 illustrates the effects, on the transmitsignal, if the HPPA were to operate beyond itscompression point. There will be spectral re-growthon both sides of the fundamental signal. Ifthe powerlevel of the re-growth exceeds the limit in Table 2,then the transmit signal will be corrupted. In otherwords, the node-B that employs a PA that isoperating beyond its compression point will transmita signal that is almost impossible to regenerate at thereceiving side. Therefore, the information sent willbe lost.

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Specifications ADSTm Daycounter

Rollet Stability Factor (K) 1.69 1.47

to

0c

D

100500

-50E -100_ -150o -200- -250= -30

.350400450

OuA Spectrum (hi

I14. 3t A17.4-I8Gitk -tt70.0

(c)

0.000 1.OOG ZOOG 3.OOG 4.OOG 5.00GFrqncy

Figure 4: W-CDMA HPPA Spectrum Analysis

To ensure that this HPPA is not operating in itsnon-linear region, its power spectum was analyzed(Figure 4). The fundamental signal is at +46 dBm,the desired power level. The second and thirdintermodulation signals are at -170 dBm and -217dBm respectively. From these result we can deducethat the HPPA is linear. Therefore, it can beimplemented in a W-CDMA Node-B. The reasonwhy linear amplifiers are important in a Node-Bapplication will be explained in the next sub-section.

5.2 Adjacent Channel Leakage Ratio(ACLR)W-CDMA power amplifiers require stringent

Adjacent Channel Leakage Ratio (ACLR). Thisfactor, together with the non-constant envelopeQPSK signal, prevents the use of high-efficiencynon-linear amplifiers [7], [8], [9], [10]. Hence theimportance of linear amplifiers in Node-Bapplication. However, implementation of linear PAsin a W-CDMA transmitter for high output powerresults in much higher power drain andimplementation cost. To compromise theshortcomings of linear amplification, the output ofthe PA is set to be higher, +46 dBm or 40 W.

To generate this high power level starting fromthe modulator is difficult Hence several stages ofPAs are used. Having them together in series bringsabout the condition where the power is being spilledover into the next channel. This parameter is calledACLR.

(a) 5

| ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~.........

al '

211S2t202125 2130 2135 21402145215S0O2155 02tO 2165FrWwA-t

C

la.

.ao..-... ... ..,....

I ~~~~~~~B,~4-----.--------- i-----.----,.-- ..X:''''''''''5.'''''-----

j5 .. .... .... ............

-25D2I15Z12D2I 21302135 21402514 1 2155 2.10021E

Ffo--GHz)

05 ........... ..... .... ...... .A .. .....

-100 __+ __y _ w*

-150-,----._-'__ _;: ,.

-250 .._____ __.. _._______.__....___._+_,~ ~~~......_............ ......

2 1S1 i202i225213021352 1402X145215D 2155 2102.115Froqu.cy(G8H

Figure 5: 3GPP FDD ACLR Measurements for HPPA: (a)Main Channel Spectrm (b) Spectrum of 1OMHz and 5MHz Lower than Main Channel (c) Spectrum of I0MHz

and 5 MHz Higher than Main Channel

Agilent application note [11] gave a briefintroduction on the history of the measurement.When it was first made public, the acronym ACPRwas used. It was called Adjacent Channel PowerRatio to refer to transmitter measurement; andAdjacent Channel Protection Ratio to refer toreceiver measurement. Ambiguity existed and the3GPP then introduced three terms, one ofthem beingACLR.

As stated in references [12], [13], the minimumACLR requirement for a W-CDMA transmitter is 45dBc between adjacent channels 5 MHz apart and 50dBc for altemate channels 10 MHz apart. However,according to [14], [15], [16], there should be greaterheadroom for PA ACLR requirements. We acceptedthe stringent specifications and our PA ACLR shouldbe 60 dBc at 5MHz and 70 dBc at 10 MHz Bydefinition, it takes 60 dB differences in power levelbetween the fundamental channel and its neighboringchannel before it is corrupted by the power spill-over. By this much power level, the trasmitter mustnot interfere with its neighboring or altematechannels.

Figure 5 shows an example of W-CDMA PAACLR measurement from ADSTI. The main channelpower level, shown in (a) is +45.70 dBm. It iscompared against 5 MHz and 10 MHz adjacentchannels power level at lower and upper frequencyband (b and c). Trace A shows the power level ofthe5MHz channel. Trace B is for 10 MHz channel. Thesimulation result is shown in Table 7.

Table 7: 3GPP FDD ACLR for PA Measurement Result

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1-

Channel Channel ACLRPower (dBm) (dBc)

Main Channel 45.70Lower 10MHz -18.82 64.53ChannelLower 5 MHz Channel -9.76 55.46Upper 10MHz -18.45 64.14ChannelUpper 5 MHz Channel -9.00 54.70

From Table 7, even though the lower and upperchannels' power level do not exactly meet the 60dBc (5 MHz) and 70 dBc (10 MHz) stated earlier,they are acceptable since they are still below thesystem's requirement [18], [19]. From this examplewe can pre-conclude that the adjacent channels musthave maximum power levels shown in Table 2 topass the ACLR requirement.

5.3 Output Third Order Intercept Point(OIP3)

After knowing the margin for adjacent channelpower spill-over, the next step is to determine whatthreshold value defines the linearity of the high-power PA. Here, the linearity factor is the third orderintercept point (OIP3). The following equations showhow ACLR help determine 01P3 for W-CDMA PA:

ACLR[5MHz] = -6OdBc

IM3 = -60 +(IM3Power)- 3(Loss) = -58dBc3

OIP3 = 46(PAPout)+ 2 + 8(PAPR) = 83dBm

(1)

Apparently, Dr. Amr (Lecturer, University ofCairo, Egypt) felt that 29 dB of headroom betweenPum and OIP3 is better than the 12 dB rule-of-thumb.We agree to this conclusion since equation I takesinto account the power level of the thirdintermodulation. It makes the ACLR - OIP3 - P1dBrelationship clearer.

5.4 Power Amplifier GainThe final parameter to look at is the cumulative

gain. The gain must be high in order to be able toamplify +10 dBm signal level to +46 dBm. TheHPPA is a two stage balance amplifier. The totaldesired gain is 36 dB. The simulated ADSTm graphin Figure 6 shows the gain result.

38

36

34

32

30

28

m40 m42 m43

..S(2Z1X111ID ...S(21X114J) ...S(2X1171)368043 36.189 1 36.

2.10 2.11 2.12 2.13 2.14 2.15 2.16 2.17 2.18 2.19 2.20

fre%GHz

Figure 6: W-CDMA HPPA Gain Simulation Result

With reference to Figure 6, the gain is almostconstant over the operating frequencies. Thiscondition is desirable for the HPPA design. Thealmost constant gain is also a result fromimplementing the balanced architecture.

Having discussed P-ldB, ACLR and OIP3, thesummarized W-CDMA PA requirement is tabulatedas shown in Table 2. These specifications must bemet in order to avoid non-linearity being introducedinto the transmit system by the PA. Higher degree ofmargin is imposed on the PA specificationscompared to the transmitter system requirements.

6. Summary

The main function of the HPPA is to providefinal amplification to the signal prior to transmission.To achieve the desired power level, the module mustbe able to support a minimum of +54 dB linearoutput power. This condition is crucial to avoidsignal compression. Despite that, the PA must be asrelatively linear as possible since it will be operatingin a QPSK modulation scheme.

The first phase in the HPPA design has beencompleted. The chosen architecture incorporatedpower preservation features. Design analysis showedacceptable results and purchasing of requiredcomponents has been done. The next phase is boardfabrication and testing purposes.

References

[1] 3rd Generation Partnership Project, TechnicalSpecification Group Radio Access Network,Base Station (BS) Radio Transmission andReception (FDD), TS 25.104, v6.8.0, 2004-12

[21 3RD Generation Partnership Project (3GPP)Technical Specification Group (TSG) RANWG4 UTRA (BS) FDD; Radio Transmissionand Reception, TS 25.141, v6.9.0, 2005-03.

[3] Mohamed K. Nezami, Method for Multi-CarrierPower Amplifier Linearization, RaytheonCompany, St. Petersburg, Florida, USA.

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o)

[4] Robert J. Baxley, G. Tong Zhou, AssessingPeak To Average Power Ratios forCommunications Applications, School ofElectrical & Computer Engineering, GeorgiaTech, Atlanta.

[51 Application Note 1325 "Performing cdma2000Measurements Today" by Agilent Technologies.

[6] Application Note 1355 "Designiing and Testing3GPP W-CDMA Base Transceiver Stations" byAgilent Technologies.

[7] Christian Olgaard, "Combining CCDF and EVMto assess 802.11 Transmitter" RfDesign.com/mag/radio_combininmgccdf evm/index.html

[8] Les Besser, Rowan Gilmore, Practical RFCircuit Design for Modem Wireless Systems,vol. II, Artech House, 2003.

[9] Frederick H. Raab, Peter Asbeck, Steve Cripps,Peter B. Kenington, Zoya B. Popovich, NickPothecary, John F. Sevick and Nathan 0. Sokal,"RF and Microwave Power Amplifier andTransmitter Technologies" Part 1-5, HighFrequency Electronics, Summit TechnicalMedia, LLC, September 2003.

[10]Application Note "QPSK ModulationDemystified" by MAXIM

[1I] Application Note 1355 "Designing and Testing3GPP W-CDMA Base Transceiver Stations" byAgilent Technologies.

[12]Wong Siew Kin, The RF Front-EndImplementation of Third Generation MobileCommunication UMTS I W-CDMATransceiver, Faculty of Engineering, MMU,2002.

[13]Information Societies Technology (IST) Reporton Design Methodology and Implementation ofa 3RD Generation W-CDMA Transceiver usimgDeep Submicron CMOS Technologies, TheLemon Project, 30oh June 2000.

[14]Application Note 1313 "Testing and Troubleshooting Digital RF CommunicationsTransmitter Design" by Agilent Technologies.

[15]3RD Generation Partnership Project (3GPP)Technical Specification Group (TSG) RANWG4 UTRA (BS) FDD; Radio Transmissionand Reception, TS 25.104, v6.8.0, 2004-12.

[16]Nikhil Deshpande, Steven Stan and MichealHurst, "ACPR Specs Place Demands on W-CDMA Base Station Amplifiers", Lead Feature,Wireless Systems Design, August 1999.

[17]Information Societies Technology (IST) Reporton Design Methodology and Implementation ofa 3R Generation W-CDMA Transceiver usingDeep Submicron CMOS Technologies, TheLemon Project, 30e June 2000.

[18]Wan Nasra Wan Firuz, "3G W-CDMA FDDTransmitter System Specifications", 3G UTRAFDD Transmitter Report, TMR&D, July 2004.

[19]G. P. Semero, David C. Vallese, "Non-LinearControl of a High-Power Transmitter", TheProceedings of the Eleventh AnnualInternational Conference on Signal ProcessingApplications & Technology 2000 (ICSPAT-2000), Dallas Texas, San Francisco, 16-19October 2000.

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