A new concept of self-aligned contact implantation for power devices

Banu Poobalan, 1,2 Kuan Yew Cheong, 1* Ung Boon Hoe,2 Resch Roland,2**

1 School of Materials and Mineral Resources Engineering, Engineering Campus, Universiti Sains Malaysia, 14300 Nibong Tebal, Seberang Perai Selatan, Penang, Malaysia,

2 Infineon Teclmologies (Kulim) Sdn Bhd Lot 10 & 1 L Jalan Hi-Tech 7, Industrial Zone Phase 2,

Kulim Hi-Tech Park, 09000, Kulim, Kedah Darul Aman, Malaysia,

* E-mail: cheong@eng,usmmy, Tel: +604-5995259, FAX: +604-594 1011

** E-mail: Roland,Resch@infineon,com, Tel: +604-4278618

Abstract

This paper discusses a new concept for the self­aligned contact implantation for Injineon power transistors, Instead of utilizing side wall spacers, which are formed by Tetraethylorthosilicate (TEOS) deposition followed by an anisotropic TEOS etch, the contact implantation is facilitated after the contact hole-etch process. By app�ving this concept, a number of process steps can be removed, which as a consequence great�v reduces the frontend production cost of a wafer. Additiona/�v, defect density baseline as well as cycle time of the wafer is significant�v reduced. Several design of experiments were performed in order to achieve the same electrical performance as compared to the original concept. Special consideration has been given on the ana�vsis of the transistor parameters, such as 'on resistance " 'threshold voltage' and 'transconductance '. The results

are presented and discussed clear�v showing the potential of the new concept.

1. Introduction

Power semiconductor devices are electronic components use as rectifiers or switches in electronic circuits. A majority of these devices are made of silicon, however other materials such as silicon carbide are already used for special applications. Examples of COllunon power transistors are Metal-Oxide­Semiconductor Field-Effect Transistors (MOSFETs), Bipolar Junction Transistors (BJTs), and Insulated Gate Bipolar Transistors (IGBTs) [I). A sufficient contact between source and drain is crucial for the functioning of tllese devices. A widely used concept to achieve this is to align the contact implantation on the poly silicon gate and source region through a spacer fonned by Tetraetllylortllosilicate (TEOS) deposition followed by an anisotropic TEOS etch. For n-type transistors tltis

contact implanatation is also referred to P++ implantation.

The advantage of having a spacer is to avoid an additional photo layer when aligning the contact implantation to tlle channel region. Additionally, the spacer is able to effectively isolate tlle contact implantation from the channel area (Figure I) and that is why tlle concept is also referred to self-aligned contact implantation. The shallow diffused P++ surface below the source region helps to reduce tlle P-base sheet resistance and its contact resistance [2). Witll the spacer concept the base length (Rbase) of the DMOS­inherent parasitic bipolar structure can be ntinimized to tlle outer most extent. Thus, no latch-up phenomenon witltin tlle specified safe operating area of the transistor will be occurred [3).

AISICu

Spacers ...... ,rt.ver ox._ 2 __ ox. Ide 1. ,/

. . -

.�.� -",-� ,' .. ��. ," , . . ",:; .. :.�;. .: , " " '-A - '_

Figure I: Cross section of power transistor device

In the present wafer fabrication process, tlle channel (boron) and the source (arsenic) is implanted before the spacer, then followed by implantation of P++. However, the deposition of tltick spacer via low pressure chemical vapour deposition (LPCVD) often increase defect density in the wafer. Moreover, ratller extensive maintenance of the tool is required.

33rd International Electronics Manufacturing Teclmology Conference 2008

Several ideas have been developed in order to replace this spacer process and eliminate its subsequent process steps (anisotropic plasma etch, furnace anneal, various cleans) from a production process. With this, the production process costs and the defect density can be reduced. Therefore, tItis is the objective of tItis manuscript to report a new concept, in wltich the P++ implantation has been perfonned after defining a contact hole and tItis allows tile spacer block to be eliminated [4].

2. EXI)erimental Procedure

Several design of experiments (DOE) were perfonned in order to acltieve the same electrical perfonnance as compared to tlle original concept. Parameters that had to be investigated were tlle source implantation dosage, P++ diffusion time. and temperature. The investigated electrical parameters are on resistance (Ron), tIrreshold voltage (Vu,), and transconductance. In addition. avalanche tests were also perfonned.

Figure 2 displays the basic process flow of tile new concept in comparison to the original (SID) spacer concept. In the original process sequence, the spacer block is perfonned subsequentIy to the structuring of poly silicon gate, channeL and source implantation. After tItis, tile P++ implantation was introduced and followed by a diffusion process. The interlayer oxide I and 2 were processed tIlen followed by contact hole pattenting and etclting process.

The new concept comprises of two major differences compared with the original process flow.

FirstIy, the spacer process is completely removed and secondly tile positioning of the P++ implantation is sltifted tlrrough tile contact hole. As a consequence, the overall source dosage and P++ diffusion conditions have to be modified.

In the first experiment, tile influence of source (arsenic) dosage was investigated whereas tile second experiment was perfonned to detennine the suitable annealing temperature and duration for the activation of implanted dopant. Furnace annealing with X condition had been carried out to confonn tlle interlayer oxide whereas Y annealing condition had perfonned to reflow the contact hole. In tile standard flow. tile P++ underwent two annealing processes with two different conditions (X and Y) whereas only one annealing (Y) was perfonned in tile new concept. The effect of tlle reduced diffusion condition was simulated witIl a professional simulation tool. Based on tile results obtained, tile definition of tile final process conditions and tIleir introduction into the new process flow was perfonned in order to evaluate the new modified spacer-free concept.

3. Results and Discussions

The first experiment was carried out to investigate tile effect of changes in tile overall source (arsenic) dosage on tile electrical parameters of the transistor. For tItis evaluation, the standard process flow

nonnalized results are presented in tltis manuscript. From tile results obtained, nonnalized values of Vu, and Ron are 1 .65 and 700 respectively for 50% of tile was used. The measured results have been divided by tile

STD Flow

2

n .

Sour"C& 1 -Al""Sanic Implantation

(STO)

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p++ Implantation (Z)

shifted into contact: hole

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Furnace Annealing (V)

Contact: Hole Plasrna Etx:hing

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I

Figure 2: Portion of the spacer fonnation process wltich shows tlle comparison between the standard flow and new concept flow

33rd International Electronics Manufacturing TeciUlology Conference 2008

results of the standard process (SID) and the standard dosage group (0.5* STD). On the other hand, the SID group value is approximately I (Figures 3 & 4). This deviation can be attributed to the reduction of source region overlapped with poly silicon gate (after diffusion) as the dosage is reduced to 0.5*STD. As a result, more voltage is required for the channel fonnation. Threshold voltage is defined as the minimum gate electrode bias requires to strongly invert the surface under the poly silicon gate and to fonn a conducting channel between the source and the drain regions [5]. The source and channel resistance increases as the dosage of arsenic in the source region is decreased to 50% of the standard Z dosage. Another factor that contributes to the increment of these parameters is the interaction of the P++ doping towards the channel region with the standard P++ implantation condition. In the case of 0.5*SID arsenic dosage and P++ implantation with spacer, the overall source dosage is affected by P++ dopants concentration (Z dosage is higher than 0.5*SID). TillS aspect can be resolved by increasing the source implantation dosage. The results clearly show that the dosage values of source can be varied from 70% of the standard dosage (0.7*SID) up to twice the standard value (2*STD) in order to obtain comparable results with the reference value.

200

OJ '" 13 1.80

g ." 1.60 0 .r:. � r=. 1.40 ." OJ .!::! 1.20 "iii E 0 Z 1.00

Overall Source dosage(cm ') Figure 3: Nonnalized threshold voltage for variation

of overall source dosage (with spacers)

The second experiment was carried out to detennine the suitable annealing diffusion condition for boron (P++) implantation into the contact hole. Before executing the experiment, simulation on P++ diffusion for SID (X+Y) and Y conditions were perfonned. Based on the profile obtained, the peak value of boron for the SID and Y conditions is approximately at 0.25 wn depth and the overall penetration depth is about 0.63 um (Figure 5). The results confinn that the profile for P++ diffusion for the standard condition has a similar profile with Y condition. (Figure 6). TIllS confinns that Y condition itself can be used to diffuse P++ as per the standard process flow. The second

experiment was to evaluate the influence of diffusion duration on X and Y (Y + 5 and 1 0 lnin) conditions with the following processes variations:

700 � c .B 550 II>

'ij � 400 o ." � 250 '" E o 100 Z

_50 L-__ � ______ � ______ �� ______ � ___

O.S-STD STD Overall Source dosage(cm'l)

Figure 4: Nonnalized on resistance for variation of overall source dosage (with spacers).

.-. 1021 ':' E � g '0 :;:; � c � 10' C 8 + + 10' � C e S .0'

000

Figure 5:

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000

Figure 6:

020 044 0110 Depth (urn)

0110

x STO(X+V)

'00

Simulation result shows P++ diffusion profile for X and SID(X+Y) diffusion conditions by using simulation tool

020 044 l

060 Depth (urn)

v

0110 '00

Simulation result shows P++ diffusion profile for Y diffusion condition.

The results of tIllS DOE reveal that the Ron and Vtl1 are marginally lower for all spacer-free groups compared with the standard group (Figures 7 & 8). TIllS can be explained by the reduction of P++ doping interaction towards channel region as the P++ is implanted into contact hole away from gate region. In

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other words, stronger P++ doping effect towards channel area occurs as P++ implantation is done with spacers. TIle increments of Y duration up to 10 min within the spacer-free groups show no significant influence on Ron and Vtl, (Figures 7 & 8), indicating that out-diffusion of the P++ is reduced in and it is sufficient to establish a contact between source and drain.

In the third DOE, the suggested target process for the new concept was evaluated in a direct comparison to the reference process. Additionally, the overall source dosage is varied from 50% to 200% of the standard value. For the activation of the P++ implantation, the Y condition was used. TIle threshold voltage is again marginally lower for the spacer-free groups compared with the standard group (Figure 9). TItis is because of the reduction of the P++ influence on the channel region as previously described. As the dopant concentration in source region is reduced (2*STD to 0.5*STD), t11e Ron values are almost comparable to the standard group (Figure 10). On the other hand, transconductance is vice versa to the Ron value (Figure II). Transconductance measures the sensitivity of drain current to the changes in gate-source voltage. It determines the current-carrying capacity of t11e device [6]. The spacer-free group with 0.75*STD and 2*STD have marginally higher transconductance compared to STD group. TItis can be explained by t11e reduction of source resistance in the spacer-free groups as P++ is implanted into t11e contact hole away from the channel region. TIle reduction of t11e on resistance attributes to the increases in current-carrying capacity of t11e device. However, the spacer-free group with 0.5*STD demonstrates marginally lower transconductance for t11e reasons that marginally ltigher source resistance with lower arsenic dosage and the reduction of source overlapping wit11 poly silicon gate, wltich eventually increases t11e channel length.

For the perfonnance of the transistors, avalanche rating is anot11er key parameter needs to be considered. TIle value of base lengt11 resistance (Rbase) is determined by t11e lengt11 of the shoulder linking the channel region to t11e P++ diffusion. As t11e P++ is implanted into the contact hole away from the channel region, the base length of the DMOS-inherent parasitic bipolar structure is increased. TIle current flowing laterally t1rrough t11e Rbase causes olunic voltage drop. If the voltage exceeds about 0.6 V. it will initiate a transistor action in the parasitic BJT. Increased Rbase needs lower reverse current to activate the parasitic BJT [6]. A ltigh increase in avalanche current destroys the device. TIlerefore the avalanche rating has to be carried out to detennine t11e range of current t11at causes t11e destruction of the device. The nonnalized avalanche current range is 1.3 to 1. 8 for the tlrree groups with P++ implantation without spacers and 1.35-1.75 for the reference group.

The nonnalized mean value is approximately 1.58 for all groups inclusive of the reference group (Figure 12). TItis clearly shows the avalanche rating is witltin the range as the modification made on P++ implantation in the process flow is still able to maintain the avalanche

current limit.

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'" o � g.98 � 1: � '" OIlS Q) � '" E 0.02 o Z

Spacer free; Spacer rree; Spacer free; X Y + Smlns Y + 10mlns

P++ DiffUSion Groups

With spacers; STO (X + Y)

Figure 7: Nonnalized threshold voltage for various P++ diffusion groups.

11�

Q) U 110 C 19 III IO!I ID It c 100 0 "0 � 0950

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Spacer free; Spacer free; Spacer free; Wltil spacers; X Y + Smlns Y + 10mlns STO ( X + Y)

P++ Diffusion Groups

Figure 8: Normalized on resistance for various P++ diffusion groups.

QJ CI 1.02

� � g 0900

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cr 0 £ 0940 ID .... £ I- 0800 "0 QJ � 0.860 10 E .... 0 0820 Z

Spacer free; Spacer free; Spacer free; STO 0.5·STD 0.75 STO 2'STO (with Spacer)

Overall Source dosage(cm j) Figure 9: Nonnalized tlrreshold voltage for various

overall source dosage.

4 33rd International Electronics Manufacturing Teclmology Conference 2008

Q) u c co ... .!!! III Q) a:: c 0 '0 Q) N

1.08

1.04

1.00

= 0.960 CO E 1... o 2 0.920

Spacer free; Spacer free; Spacer free; STD O.S*STD O.7S*STD 2*STD (with Spacer)

Overall Source dosage(cm-3) Figure 10: Nonnalized on resistance for various

overall source dosage; P++ implantation with spacer and spacer free

c: 11CS o B :J �loe � C � 096 I-'0 <II � OM ., E � 076

Spacer free; Spacer free; O.S"STD O.7S"STD

Spacer free; STO 2"STD (with Spacer)

Overall Source dosage(cm-S) Figure II: Nonnalized threshold voltage for various

overall source dosage: P++ implantation with spacer and spacer free

0.999

>- 0990 U C Q) ::J 0.900 C" � u... '?: 0.:100

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.a 0100 e 0.

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1.30 1.35 1.40 1.45 1.50 1.55 1.60 1.65 1.70 1.75 1.80 Normalized Avalanche current

Figure 12: Proability frequency vs nonnalized avalanche current for spacer free and reference group

4. Conclusion

TIle results presented in this paper clearly show that the spacer block can be successfully removed for the production of power transistors. By applying an alternative concept for the positioning of the contact implantation in the fabrication process together with the adaptation of the source implantation and diffusion conditions, a matching device perfonnance with respect to Ron, VU1, and transconductance could be attained. With tltis, tile frontend production cost of a wafer can be significantly optimized, the cycle time for a wafer in production reduced, and a lower defect density baseline established.

Acknowledgments T h e a u t h o r w o u ld lik e t o t h a n k In f i n e o n

Technolo g i e s Kul i m f o r funding t h e research.

References

(l] Muhammad H.R., Power Electronics Circuits, Devices and Applications" 3rd Edn, Pearson Prentice HalL 2004. pg 5

[2] Krislma S., "A High-Density, Self-Aligned Power MOSFET Structure Fabricated Using Sacrificial Spacer Teclmology," IEEE Trans Electron Dev., Vol.39 (1992) pp1252-1253

[3] Deboy G., Marz M., Stengl l.-P., Strack H., Tihanyi 1. and Weber H., "A new generation of ltigh voltage MOSFETs breaks tile limit line of silicon," IEEE-IEDM 98 (1998) pp. 684

[4] Hsltieh F.-I., Chang M., Chen 1., et al. "Structure and Fabrication of Power MOSFET Including Tennination Structures," Patent NO.5404040 (1 995)pp.6

[5] Barkhordarian V., "Power MOSFET Basics," International Rectifier, EI Segundo, Ca.pp.7

[6] Duncan A.G., 101m G., "Power MOSFETs Theory and Applications,"(BristoLUK,1989), pp.68.

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